ADMC331 digital inverter power supply design

1 Introduction
followed by information skills to carry out power inverter are becoming more widely used in communications, military, aviation, aerospace and other areas. Traditional power inverter multi imitate the moderation may imitate figures associated restraint system, its robustness, the complex structure, the cost is high and unlucky in product replacement. Modern power inverter being carried out toward the all-digital, intelligent and collection bias. Followed by high-function digital signal flags disposal (DSP) presentation had become capable of completion of the full digital power inverter. In this paper, the bedrock on the ADMC331 specific profiling introductions detailed use of the ADMC331 restraint at full digital power inverter. the
structural features of 2 ADMC331
ADMC331 imitate American Devices, Inc. (ADI) based on DSP motor skills temperance, internally integrated 26MIPS (million instructions per second), fixed-point digital the signal flags disposal kernel, also the internal embracing The complete motor moderation peripheral line, and then move to the user, to efficiently develop the motor sparingly invented the very favorable premise. ADMC331 the function block diagram shown in Figure 1Grid tie inverter, the primary characteristics are as follows:
● using 16-bit fixed-point ADSP-2171 kernel code with the ADSP-2100 digital signal flags dispose series is fully compatible; It has three self full function accounting units, namely: a 16-bit arithmetic / logic unit (ALU), a 32-bit multiplier-accumulator (MAC), and a 32-bit barrel shifter (SHIFTER); episodes with two self data address is (DAGs) and a strong sequential timing. And therefore can accelerate the implementation of the sequence because a system configuration of the device is a parallel construct.
● single-cycle instruction execution effort 38.5ns (external 13MHz crystal oscillator), to be completed: occurrence of the next order of address, fetch the next instruction to execute one or two data move operations to update one or two data address pointers perform an accounting operation function. http://www.gridtieinverter.de/

● Built-2k × 24 bit sequence memory ROM, 2k x 24 bit order memory RAM and 1k × 16-bit data memory RAM.
● pulse width modulation (PWM) based on the midpoint of a three-phase 16 attack, high-precision PWM signal flags disposal minimum expenditure sensitive programming occurs.
● the channel frequency programmable with 2-channel 8-bit the assistant pulse width modulation (AUXPWM).
● seven Σ-Δ A / D conversion channel, the maximum resolution of 12 bits, the maximum sampling frequency of up to 32.5kHz.
● has 24 programmable digital input and output (PIO) port can be set to input or output alone, supporting the morphological changes in infix.
● to supply 2 double-buffered Synchronous Serial Port (SPORT0, SPORT1), to be completed by the communication between the serial communication and multi disposal.
● 16 with timely infix watchdog time is.
● order of internal memory ROM curing some of the applicable order, facilitating the order of the system design, and cut the order of the digital restraint system accounting effort.

3 Examples of use
ADMC331 composed of fully digital inverter power structure shown in Figure 2.
signal flags the 3.1 PWM constitute
the ordinary full digital power inverter is necessary for to 4 Road accurate PWM-time signal flags to drive IGBT inverter bridge, this also drive each power tube PWM signal flags necessary for a conduction delay, in order to avoid the upper and lower leg power switch is turned on breaking the system. Occurrence of the PWM signal flags is completed by the ADMC331 within PWM moderation is the ADMC331 the PWM attack units in sensitivity and programmability fully digital PWM method differences of approach to be contentpower inverter. Figure 3 is a function block diagram of the three-phase PWM restraint by ADMC331. The the
ADMC331 PWM unit is to establish the foundation of a three-phase time is self, by three to determine the cycle storage to moderation, each cycle storage restraint on the PWM output. The restraint required DSP sequence can be prepared in accordance with the requirements of the use of premises, as well as the needs of the PWM. Figure PWMPOL door gate drive circuit logic and structure to select the PWM output polarity of each channel PWM output signal flags that can be passed through the self-reliance so can be stored the device PWMSEG to resolution output enable or to stop. PWMTRIP circuit hardware maintenance when this pin is low, often, the entire system is reset without a premise for maintenance of the entire circuit. In addition to clock output the of signal flags CLKOUT and PWM synchronization signal flags PWMSYNC.