circuit diagram (1)
works:
Here we will detail the working principle of the inverter.
, square wave generation
CD4069 constitute a square wave signal generator. R1 in the circuit is a compensation resistor, used to improve the oscillation frequency due to changes in the supply voltage caused by instability. The shock of the circuit is completed through the capacitor C1 is charged and discharged. The oscillation frequency f = 1/2.2RC. The maximum frequency of the circuit as shown: fmax = 1/2.2x103x2.2x10-6 = 62.6Hz,power inverter, the minimum frequency fmin = 1/2.2x4.3x103x2.2x10-6 = 48.0Hz. Due to the errors of the components, the actual value will be slightly different. Other unwanted fat phase, the input connected to ground to avoid the influence of other circuits.
Figure 2
, FET drive circuits.
Since the maximum amplitude of the oscillation signal output voltage of the square wave signal generator is 0 ~ 5V, the full drive power switching circuit, where TR1, TR2 of the oscillation signal voltage is amplified to 0 ~~ 12V. As shown in Figure 3.
Figure 3
, FET power switch circuit.
FET is the core of the device, before in Introducing the part works, briefly explain MOS FET works.
MOS FET has also been referred to as MOS FET, i.e., Metal Oxide Semiconductor Field Effect Transistor (metal oxide semiconductor FET) Abbreviation. General depletion mode and enhanced two. This article uses the enhanced MOS FET, its internal structure is shown in Figure 4. It can be divided into an NPN and PNP type,Grid tie inverter. The NPN type usually referred to as the N-channel type and PNP type usually known as the P-channel type. Figure tube can be seen, the N-channel type field effect its source and drain connected to the N-type semiconductor, the same tube for the P-channel FET with its source and drain connected to the P-type semiconductor. . We know that the the general transistor is the current output by the input current control. But for the FET, the output current is controlled by the input voltage (or field voltage) can be considered that the input current is minimal or no input current, which makes the device has a high input impedance, while this is we call The reason for the FET.
Figure 4
explain MOS FET works, let's look at the process of a P-N junction diode only. Shown in Figure 5, we know that the forward voltage (P Termination positive electrode, N termination negative), the diode conducts the current through the PN junction diode plus. This is due to the positive voltage at the end of the P-type semiconductor, the negative electrons within the N-type semiconductor is attracted flock applied a positive voltage of the P-type semiconductor side, and positrons within the P-type semiconductor side toward the N-type semiconductor side movement, thereby forming a conduction current. Similarly, when the the diode plus reverse voltage (P Termination negative, N terminating positive electrode, when the P-type semiconductor side to a negative voltage, n electrons are gathered in the p-type semiconductor side, the negative electrons are gathered in the N-type semiconductor side, the electrons do not move, no current flows through the PN junction diode cutoff.
Figure 5
For FET (Figure 6), when no voltage in the gate, with the previous analysis, not a current flows between the source and the drain, the FET is in the OFF state (FIG. 6a). When a positive voltage is applied to the N-channel MOS FET gate, due to the effect of electric field, the negative electrons of the source and drain of the N-type semiconductor is attracted and flock to the gate, but due to The oxide film of the barrier, making electronic aggregation (Figure 6B) in between the two N-channel P-type semiconductor, thereby forming a current, so that the conduction between the source and drain. We can also imagine a ditch between the two N-type semiconductor, the establishment of the gate voltage between for them take a bridge, the bridge's size is determined by the gate voltage. Figure 8 shows the working process of the P-channel FET, similar to how it works will not repeat it here.
Figure 6
briefly below the working process of the application circuit of C-MOS FET (Enhanced MOS FET) (see Figure 8). The circuit will be an enhancement-type P-channel MOS field colonels and an enhancement-type N-channel MOS FET used in combination. When the input is the bottom level, the P-channel MOS FET output and the positive power supply is turned on. When the input is high, N-channel MOS FET is turned on, output terminal and the power turned on,power inverter. In this circuit, the P-channel MOS FET and the N-channel FET is always in the opposite state, the opposite phase input terminal and an output terminal. Through this work we can get a large current output. Due to leakage currents at the same time, so that the gate voltage is not to 0V, typically the gate voltage is less than 1V to 2V, the MOS FET i.e. off. The different FET turn-off voltage is slightly different. Think so, so that the circuit will not short out power to two simultaneous conduction.
Figure 8
Figure 9
above analysis we can draw the MOS FET schematic part of the work process (see Figure 9). The working principle is the same as the foregoing, such low voltage, high current, a frequency of 50Hz alternating signals through the low voltage winding of the transformer, the high-pressure side of the transformer to induce a high-voltage AC voltage, the completion of the DC to AC conversion. Note here that, in certain circumstances, such as the oscillation portion stop working when the low-voltage side of the transformer is sometimes there will be a large current through, so that the fuse of the circuit can not be omitted, or shorting.
circuit board shown in Figure 11. Elements may be used by referring to Figure 12. Secondary inverter transformer used for 12V and current of 10A, the primary a refined power transformer voltage of 220V. The maximum drain current of the P-channel MOS FET (2SJ471) 30A, when the FET, the resistance between the drain - source 25 mOhm. By 10A current will 2.5W power consumption. N-channel MOS FET (2SK2956) maximum drain current of 50A, FET, the drain - source resistance of 7 milliohms, through 10A current power consumption of 0.7W,www.12vgridtiepowerinverters.com. Thus we have seen that in the same working current circumstances, The 2SJ471 fever about 2SK2956 4 times. Therefore, in considering the radiator should pay attention to this point. Figure 13 shows an inverter FETs location distribution and connection on the radiator (100mm × 100mm × 17mm) that are described in this article. The FET switch state heat will not be great, for security reasons radiator choice here Shaopian.
Figure 11
Figure 12
Figure 13
Figure 14
inverter performance test
test circuit is shown in Figure 15. Test input power 12V car battery with low internal resistance, discharge current (generally greater than 100A), and provides plenty of input power for the circuit. The test with a load of an ordinary electric bulb. The test method is by changing the size of the load, and measuring the input current at this time, the voltage and output voltage. Their test results, see the curve of the voltage, current diagram (Figure 15a). It can be seen that the output voltage with the increase of the load decreases, the consumed power of the lamp with the voltage change. We also find out the relationship between the output voltage and power can be calculated. But actually changed due to electrical resistance of the bulb with by raising both ends of the voltage change and the output voltage, the current does not be a sine wave, so this calculation can only be regarded as estimates. Load is 60W light bulb, for example:
Figure 15
Figure 16,17
assumed that the resistance of the bulb does not change with the voltage change. R lamps = V2 / W = 2102/60 = 735Ω, so the voltage of 208V, W = V2 / R = 2082/735 = 58.9W. Which can be converted into a voltage and power relations. Pass the test, we found that when the output power is about 100W, input current of 10A. The output voltage is 200V. The inverter power efficiency characteristics shown in Figure 15b,Grid tie inverter. Figure 16 is an inverter continuous 100W load, FET, the temperature rise of FIG. The output waveform diagram for the production of 17 different load reference.
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